This week at ISSCC 2005, IBM/Sony/Toshiba released some preliminary information on their new Cell processor, which is destined to be used in Sony's PlayStation 3, to be released in 2006.
What is Cell?
1) Cell has a single 64-bit PowerPC in-order core with supports both VMX (aka Altivec) and simultaneous multithreading (SMT). Contrary to rumours, it is not based off the POWER5 core. Rather, it is based on a previously unused design discussed at ISSCC 2000, but likely borrows some design concepts from POWER5. Power utilization of the PowerPC core is unknown.
2) Cell also has 8 independent "synergistic processing elements" (SPE) which function akin to complex DSP cores. Each SPE has its own local 256 KB memory. With 8 cores, and another 512 KB of L2 cache, that's a total of 2.5 MB of on-die memory.
3) Cell's clock speed for the PS3 is unknown, but Cell apparently can hit 5.2 GHz at 1.3 V. Power utilization is of course high at that level, with each SPE drawing around 12 Watts, but at 4 GHz it can probably run at 1.1 V. At this level, each SPE may draw only 4 Watts.
4) Cell's 9 cores are all connected by an "element interface bus" (EIB) which runs at half of the clock speed. The EIB also connects to the 512 KB L2 cache, the bus interface controller (BIC), and the dual XDR memory controller. In other words, the on-chip communications is very fast between the various cores and controllers, at 2 GHz for a 4 GHz chip.
5) Cell has 234 million transistors, and fabricated on the 90 nm process, measures 221 mm². However, in order to reduce die area, power utilization, and cost, it's quite possible that a PS3 version of Cell would have a reduced number of SPE cores, or would be fabriated on the 65 nm process, or both.
In essence, this Cell chip is a new and lean PowerPC chip with Altivec support, and a bunch of non-Altivec vector CPUs tacked onto it (each with its own local memory), all connected by a very fast bus.
What does this mean for Apple?
Quite frankly, I'm not sure. It's a very high-clocked chip, and the PowerPC/Altivec core could likely be supported easily in OS X. However, the SPE cores would be new for Apple, and at this point might just be extra baggage. And considering the amount of die real estate they consume, that baggage would be awfully expensive.
If Apple were to consider using this chip complete with the SPE cores, it would take a significant amount of work to get everything in place in Apple's OS and software, as well as to get the developers on board. Without the SPE cores (and the funky busses) the chip seems like a more traditional design, but with supposedly some potentially significant limitations, despite the high clock speed. (Supposedly, because I'm not an engineer.)
Given the above, it still seems to me that the more likely scenario is that Apple will continue to use the G5 970 series chips, with higher clock speeds and further optimizations for lower power utilization, and perhaps dual cores and increased cache. Eventual stripped-down SMT-capable POWER5 cores with an integrated memory controller and Altivec would also be used.
Cell presents an interesting proposition for Apple for use in the future, but it doesn't seem to be in the cards in the near term.
One more thing... Rumours suggest that Xenon, the chip in Microsoft's Xbox 2, also uses a similar PowerPC core, except that Xenon has 3 of them, and no SPE cores. This would mean that IBM is selling this Power Architecture core design to at least two major competing customers, but is letting them decide on how the overall chip should be implemented.