iMac G5 Developer Note available

Apple has now published the Developer Note for the new G5 iMac.

There are a few interesting things in the note that weren't known previously:

1) The iMac G5 supports dual-channel memory:

Additional DIMMs can be installed. The combined memory of all of the DIMMs installed is configured as a contiguous array of memory. The throughput of the 400 MHz memory bus is dependent on the DIMMs installed. If only one DIMM is installed, the memory bus is 64-bit. If two non-identical DIMMs are installed, there are two 64–bit memory buses. If two identical DIMMs are installed, the memory bus is 128-bit. Identical DIMM pairs have the same size and composition and provide the fastest and most efficient throughput.

This means that if you install two identical DIMMS, you get twice the theoretical throughput. It also means the system bus speed may become the bottleneck.

2) The iMac G5 may support DDR333:

The RAM expansion slots accept 184-pin DDR SDRAM DIMMs that are 2.5 volt, unbuffered, 8-byte, nonparity, and DDR400-compliant (PC3200). The iMac G5 only supports DIMMs up to 1.25” in height...

DDR266 (PC2200) or slower DIMMs do not work in the iMac G5 computer.

If the iMac G5 does support DDR333, then it would support dual-channel DDR333. Theoretically, in this configuration memory bandwidth would still be faster than system bus bandwidth, at least in ideal conditions. Theory aside, support for dual-channel DDR333 would make DDR333 memory in an iMac G5 a reasonable compromise for those on a budget and who already have DDR333 memory.

3) The iMac G5 uses a 90 nm system controller:

The processor bus is an up to 600 MHz bus connecting the processor to the U3L IC. The bus has 32-bit wide data running in both directions. The processor has 42-bit wide addresses.

The iMac G5 system controller is built with 90-nanometer SOI technology.

One wonders if this was one reason for the new iMac's delay.